(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) driving method.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. Among the flat panel devices, the plasma displays have better luminance and light emission efficiency as compared to the other types of flat panel devices, and also have wider view angles. Therefore, the plasma displays have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
The plasma display is a flat display that uses plasma generated via a gas discharge process to display characters or images. Depending on its size, the plasma display can include tens to millions of pixels that are provided thereon in a matrix format. According to supplied driving voltage waveforms and discharge cell structures, plasma displays can be categorized into direct current (DC) plasma displays and alternating current (AC) plasma displays.
Since the DC plasma displays have electrodes exposed in the discharge space without insulation, they allow a current to flow in the discharge space while the voltage is supplied, and therefore they are problematic in that they require resistors for current restriction. On the other hand, since the AC plasma displays have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, the AC plasma displays have a longer lifespan than the DC plasma displays.
FIG. 1 shows a partial perspective view of an AC PDP, and FIG. 2 shows a cross-sectional view of the PDP shown in FIG. 1.
As shown in FIGS. 1 and 2, X electrode 3 and Y electrode 4, made of transparent conductive matter and disposed over dielectric layer 14 and protection film 15, are provided in parallel and form a pair with each other under first glass substrate 11. Metallic bus electrodes 6 are respectively formed on the surfaces of X and Y electrodes 3 and 4.
A plurality of address electrodes 5 covered with dielectric layer 14′ are installed on second glass substrate 12. Barrier ribs 17 are formed on dielectric layer 14′ between address electrodes 5, and in parallel with address electrodes 5. Phosphors 18 are formed on the surface of dielectric layer 14′ between barrier ribs 17. First and second glass substrates 11, 12 are provided facing each other with discharge space 19 between first and second glass substrates 11, 12 so that Y electrode 4 and the X electrode 3 may respectively cross address electrodes 5. An address electrode of the address electrode 5 and discharge space 19 formed at a crossing part of Y electrode 4 and X electrode 3 form schematically indicated discharge cell 20.
FIG. 3 shows a conventional PDP electrode arrangement diagram. The conventional PDP electrodes have an m×n matrix configuration. Address electrodes A1 to Am are arranged in a column direction, and Y electrodes Y1 to Yn and X electrodes X1 to Xn are alternately arranged in a row direction. Discharge cell 20 shown in FIG. 3 substantially corresponds to discharge cell 20 shown in FIG. 1.
FIG. 4 shows a conventional PDP driving waveform diagram. In a conventional PDP, one frame is divided into a plurality of subfields that are combined to express a gray scale. Each subfield according to the conventional PDP method shown in FIG. 4 includes a reset period, an address period, and a sustain period. The reset period erases wall charges formed during a previous sustain discharge, and sets up new wall charges in order to stably perform functions in a next address period. In the addressing period, the cells that are turned on and the cells that are not turned on in a panel are selected, and wall charges are accumulated on the cells that are turned on (i.e., the addressed cells). In the sustain period, discharge for actually displaying pictures on the addressed cells is performed by alternately applying a sustain discharge voltage to the X and Y electrodes.
Operations of the conventional reset period of the conventional PDP driving method will now be described in more detail. As shown in FIG. 4, the reset period includes an erase period (I), a Y ramp rising period (II), and a Y ramp falling period (III).
(1) Erase Period (I)
While the X electrode is biased with a constant potential of Vbias, a falling ramp which slowly falls from a sustain discharge voltage of Vs to a ground potential (or 0V) is applied to the Y electrode, and the wall charges formed in the sustain period are eliminated.
(2) Y Ramp Rising Period (II)
During this period, the address electrode (not shown) and the X electrode are maintained at 0V, and a ramp voltage gradually rising from the voltage of Vs to the voltage of Vset is applied to the Y electrode. While the ramp voltage rises, a weak reset discharge is generated on all the discharge cells from the Y electrode to the address electrode and the X electrode. As a result, the (−) wall charges are accumulated on the Y electrode, and concurrently, the (+) wall charges are accumulated on the address electrode and the X electrode.
(3) Y Ramp Falling Period (III)
In the latter part of the reset period, a ramp voltage that gradually falls from the voltage of Vs to the 0V is applied to the Y electrode under the state that the X electrode maintains the constant voltage of Vbias. While the ramp voltage falls, a weak reset discharge is generated again at all the discharge cells.
In the sustain discharge period, the same sustain discharge voltage Vs is alternately applied to the X and Y electrodes to perform a sustain discharge for displaying actual images on the addressed cells. In this instance, it is desirable to apply symmetric waveforms to the X and Y electrodes during the sustain discharge period.
However, a circuit for driving the Y electrode is different from a circuit for driving the X electrode since a waveform applied to the Y electrode (a waveform for resetting and scanning is additionally applied to the Y electrode) is different from a waveform applied to the X electrode in the reset period of the conventional PDP. Accordingly, the driving circuits of the X and Y electrodes are not impedance-matched, the waveform alternately applied to the X and Y electrodes in the sustain discharge period is distorted, and a bad discharge is generated.
Also, a problematic (or weak) discharge may be generated due to insufficient priming particles generated in the discharge cell when the first (or initial) sustain discharge pulse is applied after the address period in the conventional PDP.